UCC27511AQDBVRQ1 TI
Beszerezhető |
UCC27511AQDBVRQ1 TI
• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
• Low-Cost Gate-Driver Device Offering Superior Replacement of NPN and PNP Discrete Solutions
• 4-A Peak Source and 8-A Peak Sink Asymmetrical Drive
• Strong Sink Current Offers Enhanced Immunity Against Miller Turnon
• Split Output Configuration (Allows Easy and Independent Adjustment of Turnon and Turnoff Speeds) in the UCC27511A-Q1
• Fast Propagation Delays (13-ns typical)
• Fast Rise and Fall Times (9-ns and 7-ns typical)
• 4.5 to 18-V Single Supply Range
• Outputs Held Low During VDD UVLO (Ensures Glitch-Free Operation at Power Up and Power Down)
• TTL and CMOS Compatible Input-Logic Threshold (Independent of Supply Voltage)
• Hysteretic-Logic Thresholds for High-Noise Immunity
• Dual-Input Design (Choice of an Inverting (IN– Pin) or Non-Inverting (IN+ Pin) Driver Configuration)
– Unused Input Pin can be Used for Enable or Disable Function
• Output Held Low when Input Pins are Floating
• Input Pin Absolute Maximum Voltage Levels Not Restricted by VDD Pin Bias Supply Voltage
• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
• Low-Cost Gate-Driver Device Offering Superior Replacement of NPN and PNP Discrete Solutions
• 4-A Peak Source and 8-A Peak Sink Asymmetrical Drive
• Strong Sink Current Offers Enhanced Immunity Against Miller Turnon
• Split Output Configuration (Allows Easy and Independent Adjustment of Turnon and Turnoff Speeds) in the UCC27511A-Q1
• Fast Propagation Delays (13-ns typical)
• Fast Rise and Fall Times (9-ns and 7-ns typical)
• 4.5 to 18-V Single Supply Range
• Outputs Held Low During VDD UVLO (Ensures Glitch-Free Operation at Power Up and Power Down)
• TTL and CMOS Compatible Input-Logic Threshold (Independent of Supply Voltage)
• Hysteretic-Logic Thresholds for High-Noise Immunity
• Dual-Input Design (Choice of an Inverting (IN– Pin) or Non-Inverting (IN+ Pin) Driver Configuration)
– Unused Input Pin can be Used for Enable or Disable Function
• Output Held Low when Input Pins are Floating
• Input Pin Absolute Maximum Voltage Levels Not Restricted by VDD Pin Bias Supply Voltage
Please make sure your contact information is correct. Your message will be sent directly to the recipient(s) and will not be publicly displayed. We will never distribute or sell your personal information to third parties without your express permission.